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1 of 11 081800 features real time clock counts seconds, minutes, hours, date of the month, month, day of the week, and year with leap year compensation valid up to 2100 56 byte nonvolatile ram for data storage 2-wire serial interface programmable squarewave output signal automatic power-fail detect and switch circuitry consumes less than 500 na in battery backup mode with oscillator running optional industrial temperature range -40c to +85c available in 8-pin dip or soic recognized by underwriters laboratory ordering information DS1307 8-pin dip DS1307z 8-pin soic (150 mil) DS1307n 8-pin dip (industrial) DS1307zn 8-pin soic (industrial) pin assignment pin description v cc - primary power supply x1, x2 - 32.768 khz crystal connection v bat - +3v battery input gnd - ground sda - serial data scl - serial clock sqw/out - square wave/output driver description the DS1307 serial real time clock is a low power, full bcd clock/calendar plus 56 bytes of nonvolatile sram. address and data are transferred serially via a 2-wire bi-directional bus. the clock/calendar provides seconds, minutes, hours, day, date, month, and year information. the end of the month date is automatically adjusted for months with less than 31 days, including corrections for leap year. the clock operates in either the 24-hour or 12-hour format with am/pm indicator. the DS1307 has a built-in power sense circuit which detects power failures and automatically switches to the battery supply. DS1307 64 x 8 serial real time clock DS1307z 8-pin soic (150 mil) DS1307 8-pin dip (300 mil) x1 x2 v bat gnd v cc sqw/out scl l 2 3 4 8 7 6 5 sda l 2 3 4 8 7 6 5 x1 x2 v bat gnd v cc sqw/out scl sda tiger electronic co.,ltd
DS1307 2 of 11 operation the DS1307 operates as a slave device on the serial bus. access is obtained by implementing a start condition and providing a device identification code followed by a register address. subsequent registers can be accessed sequentially until a stop condition is executed. when v cc falls below 1.25 x v bat the device terminates an access in progress and resets the device address counter. inputs to the device will not be recognized at this time to prevent erroneous data from being written to the device from an out of tolerance system. when v cc falls below v bat the device switches into a low current battery backup mode. upon power up, the device switches from battery to v cc when v cc is greater than v bat +0.2v and recognizes inputs when v cc is greater than 1.25 x v bat . the block diagram in figure 1 shows the main elements of the serial real time clock. DS1307 block diagram figure 1 signal descriptions v cc , gnd - dc power is provided to the device on these pins. v cc is the +5 volt input. when 5 volts is applied within normal limits, the device is fully accessible and data can be written and read. when a 3-volt battery is connected to the device and v cc is below 1.25 x v bat , reads and writes are inhibited. however, the timekeeping function continues unaffected by the lower input voltage. as v cc falls below v bat the ram and timekeeper are switched over to the external power supply (nominal 3.0v dc) at v bat . v bat - battery input for any standard 3-volt lithium cell or other energy source. battery voltage must be held between 2.0 and 3.5 volts for proper operation. the nominal write protect trip point voltage at which access to the real time clock and user ram is denied is set by the internal circuitry as 1.25 x v bat nominal. a lithium battery with 48 mahr or greater will back up the DS1307 for more than 10 years in the absence of power at 25 degrees c.
DS1307 3 of 11 scl (serial clock input) - scl is used to synchronize data movement on the serial interface. sda (serial data input/output) - sda is the input/output pin for the 2-wire serial interface. the sda pin is open drain which requires an external pullup resistor. sqw/out (square wave/ output driver) - when enabled, the sqwe bit set to 1, the sqw/out pin outputs one of four square wave frequencies (1 hz, 4 khz, 8 khz, 32 khz). the sqw/out pin is open drain which requires an external pullup resistor. sqw/out will operate with either vcc or vbat applied. x1, x2 - connections for a standard 32.768 khz quartz crystal. the internal oscillator circuitry is designed for operation with a crystal having a specified load capacitance (cl) of 12.5 pf. for more information on crystal selection and crystal layout considerations, please consult application note 58, ?crystal considerations with dallas real time clocks.? the DS1307 can also be driven by an external 32.768 khz oscillator. in this configuration, the x1 pin is connected to the external oscillator signal and the x2 pin is floated. please review application note 95, ?interfacing the DS1307 with a 8051-compatible microcontroller? for additional information. rtc and ram address map the address map for the rtc and ram registers of the DS1307 is shown in figure 2. the real time clock registers are located in address locations 00h to 07h. the ram registers are located in address locations 08h to 3fh. during a multi-byte access, when the address pointer reaches 3fh, the end of ram space, it wraps around to location 00h, the beginning of the clock space. DS1307 address map figure 2 clock and calendar the time and calendar information is obtained by reading the appropriate register bytes. the real time clock registers are illustrated in figure 3. the time and calendar are set or initialized by writing the appropriate register bytes. the contents of the time and calendar registers are in the binary-coded decimal (bcd) format. bit 7 of register 0 is the clock halt (ch) bit. when this bit is set to a 1, the oscillator is disabled. when cleared to a 0, the oscillator is enabled. please note that the initial power on state of all registers is not defined. therefore it is important to enable the oscillator (ch bit=0) during initial configuration. seconds minutes hours day date month year control ram 56 x 8 00h 07h 08h 3fh
DS1307 4 of 11 the DS1307 can be run in either 12-hour or 24-hour mode. bit 6 of the hours register is defined as the 12- or 24-hour mode select bit. when high, the 12-hour mode is selected. in the 12-hour mode, bit 5 is the am/pm bit with logic high being pm. in the 24-hour mode, bit 5 is the second 10 hour bit (20- 23 hours). on a 2-wire start, the current time is transferred to a second set of registers. the time information is read from these secondary registers, while the clock may continue to run. this eliminates the need to re- read the registers in case of an update of the main registers during a read. DS1307 timekeeper registers figure 3 control register the DS1307 control register is used to control the operation of the sqw/out pin. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 out x x sqwe x x rs1 rs0 out (output control): this bit controls the output level of the sqw/out pin when the square wave output is disabled. if sqwe=0, the logic level on the sqw/out pin is 1 if out=1 and is 0 if out=0. sqwe (square wave enable): this bit, when set to a logic 1, will enable the oscillator output. the frequency of the square wave output depends upon the value of the rs0 and rs1 bits. rs (rate select): these bits control the frequency of the square wave output when the square wave output has been enabled. table 1 lists the square wave frequencies that can be selected with the rs bits. squarewave output frequency table 1 rs1 rs0 sqw output frequency 00 1 hz 0 1 4.096 khz 1 0 8.192 khz 1 1 32.768 khz
DS1307 5 of 11 2-wire serial data bus the DS1307 supports a bi-directional 2-wire bus and data transmission protocol. a device that sends data onto the bus is defined as a transmitter and a device receiving data as a receiver. the device that controls the message is called a master. the devices that are controlled by the master are referred to as slaves. the bus must be controlled by a master device which generates the serial clock (scl), controls the bus access, and generates the start and stop conditions. the DS1307 operates as a slave on the 2-wire bus. a typical bus configuration using this 2-wire protocol is show in figure 4. typical 2-wire bus configuration figure 4 figures 5, 6, and 7 detail how data is transferred on the 2-wire bus. data transfer may be initiated only when the bus is not busy. during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be interpreted as control signals. accordingly, the following bus conditions have been defined: bus not busy: both data and clock lines remain high. start data transfer: a change in the state of the data line, from high to low, while the clock is high, defines a start condition. stop data transfer: a change in the state of the data line, from low to high, while the clock line is high, defines the stop condition. data valid: the state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line must be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated with a stop condition. the number of data bytes transferred between start and stop conditions is not limited, and is determined by the master device. the information is transferred byte-wise and each receiver acknowledges with a ninth bit. within the 2-wire bus specifications a regular mode (100 khz clock rate) and a fast mode (400 khz clock rate) are defined. the DS1307 operates in the regular mode (100 khz) only.
DS1307 6 of 11 acknowledge: each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. the master device must generate an extra clock pulse which is associated with this acknowledge bit. a device that acknowledges must pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge related clock pulse. of course, setup and hold times must be taken into account. a master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. in this case, the slave must leave the data line high to enable the master to generate the stop condition. data transfer on 2-wire serial bus figure 5 depending upon the state of the r/ w bit, two types of data transfer are possible: 1. data transfer from a master transmitter to a slave receiver. the first byte transmitted by the master is the slave address. next follows a number of data bytes. the slave returns an acknowledge bit after each received byte. data is transferred with the most significant bit (msb) first. 2. data transfer from a slave transmitter to a master receiver. the first byte (the slave address) is transmitted by the master. the slave then returns an acknowledge bit. this is followed by the slave transmitting a number of data bytes. the master returns an acknowledge bit after all received bytes other than the last byte. at the end of the last received byte, a ?not acknowledge? is returned. the master device generates all of the serial clock pulses and the start and stop conditions. a transfer is ended with a stop condition or with a repeated start condition. since a repeated start condition is also the beginning of the next serial transfer, the bus will not be released. data is transferred with the most significant bit (msb) first.
DS1307 7 of 11 the DS1307 may operate in the following two modes: 1. slave receiver mode (DS1307 write mode): serial data and clock are received through sda and scl. after each byte is received an acknowledge bit is transmitted. start and stop conditions are recognized as the beginning and end of a serial transfer. address recognition is performed by hardware after reception of the slave address and *direction bit (see figure 6). the address byte is the first byte received after the start condition is generated by the master. the address byte contains the 7 bit DS1307 address, which is 1101000, followed by the *direction bit (r/ w ) which, for a write, is a 0. after receiving and decoding the address byte the device outputs an acknowledge on the sda line. after the DS1307 acknowledges the slave address + write bit, the master transmits a register address to the DS1307 this will set the register pointer on the DS1307. the master will then begin transmitting each byte of data with the DS1307 acknowledging each byte received. the master will generate a stop condition to terminate the data write. data write - slave receiver mode figure 6 2. slave transmitter mode (DS1307 read mode): the first byte is received and handled as in the slave receiver mode. however, in this mode, the *direction bit will indicate that the transfer direction is reversed. serial data is transmitted on sda by the DS1307 while the serial clock is input on scl. start and stop conditions are recognized as the beginning and end of a serial transfer (see figure 7). the address byte is the first byte received after the start condition is generated by the master. the address byte contains the 7-bit DS1307 address, which is 1101000, followed by the *direction bit (r/ w ) which, for a read, is a 1. after receiving and decoding the address byte the device inputs an acknowledge on the sda line. the DS1307 then begins to transmit data starting with the register address pointed to by the register pointer. if the register pointer is not written to before the initiation of a read mode the first address that is read is the last one stored in the register pointer. the DS1307 must receive a not acknowledge to end a read. data read - slave transmitter mode figure 7
DS1307 8 of 11 absolute maximum ratings* voltage on any pin relative to ground -0.5v to +7.0v operating temperature 0c to 70c (-40c to 85c for industrial) storage temperature -55c to +125c soldering temperature 260c for 10 seconds dip see jpc/jedec standard j-std-020a for surface mount devices * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. recommended dc operating conditions (0 parameter symbol min typ max units notes supply voltage v cc 4.5 5.0 5.5 v 1 logic 1 v ih 2.2 v cc +0.3 v 1 logic 0 v il -0.3 +0.8 v 1 v bat battery voltage v bat 2.0 3.5 v 1 dc electrical characteristics (0 parameter symbol min typ max units notes input leakage i li 1 a 10 i/o leakage i lo 1 a 11 logic 0 output v ol 0.4 v 2 active supply current i cca 1.5 ma 9 standby current i ccs 200 a 3 battery current (osc on); sqw/out off i bat1 300 500 na 4 battery current (osc on); sqw/out on (32 khz) i bat2 480 800 na 4
DS1307 9 of 11 ac electrical characteristics (0 parameter symbol min typ max units notes scl clock frequency f scl 0 100 khz bus free time between a stop and start condition t buf 4.7 s hold time (repeated) start condition t hd:sta 4.0 s 5 low period of scl clock t low 4.7 s high period of scl clock t high 4.0 s set-up time for a repeated start condition t su:sta 4.7 s data hold time t hd:dat 0 s 6, 7 data set-up time t su:dat 250 ns rise time of both sda and scl signals t r 1000 ns fall time of both sda and scl signals t f 300 ns set-up time for stop condition t su:sto 4.7 s capacitive load for each bus line c b 400 pf 8 i/o capacitance c i/o 10 pf crystal specified load capacitance 12.5 pf notes: 1. all voltages are referenced to ground. 2. logic zero voltages are specified at a sink current of 5 ma at v cc =4.5v, v ol =gnd for capacitive loads. 3. i ccs specified with v cc =5.0v and sda, scl=5.0v. 4. v cc =0v, v bat =3v. 5. after this period, the first clock pulse is generated. 6. a device must internally provide a hold time of at least 300 ns for the sda signal (referred to the v ihmin of the scl signal) in order to bridge the undefined region of the falling edge of scl. 7. the maximum t hd:dat has only to be met if the device does not stretch the low period (t low ) of the scl signal. 8. c b - total capacitance of one bus line in pf. 9. i cca - scl clocking at max frequency = 100 khz. 10. scl only. 11. sda and sqw/out
DS1307 10 of 11 timing diagram figure 8 DS1307 64 x 8 serial real time clock 8-pin dip mechanical dimensions pkg 8-pin dim min max a in. mm 0.360 9.14 0.400 10.16 b in. mm 0.240 6.10 0.260 6.60 c in. mm 0.120 3.05 0.140 3.56 d in. mm 0.300 7.62 0.325 8.26 e in. mm 0.015 0.38 0.040 1.02 f in. mm 0.120 3.04 0.140 3.56 g in. mm 0.090 2.29 0.110 2.79 h in. mm 0.320 8.13 0.370 9.40 j in. mm 0.008 0.20 0.012 0.30 k in. mm 0.015 0.38 0.021 0.53
DS1307 11 of 11 DS1307z 64 x 8 serial real time clock 8-pin soic (150-mil) mechanical dimensions pkg 8-pin (150 mil) dim min max a in. mm 0.188 4.78 0.196 4.98 b in. mm 0.150 3.81 0.158 4.01 c in. mm 0.048 1.22 0.062 1.57 e in. mm 0.004 0.10 0.010 0.25 f in. mm 0.053 1.35 0.069 1.75 g in. mm 0.050 bsc 1.27 bsc h in. mm 0.230 5.84 0.244 6.20 j in. mm 0.007 0.18 0.011 0.28 k in. mm 0.012 0.30 0.020 0.51 l in. mm 0.016 0.41 0.050 1.27 phi 0 56-g2008-001

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